Electronic data processor



Dec. l5, 1964 C. H. PROPSTER, JR.. ETAL ELECTRONIC DATA PROCESSOR Filed Dec. 9. 1960 :56 Sheets-Sheet l 01472 TFACKS Dec. l5, 1964 c. H. PRoPsTER, JR., ETAL 3,161,856

ELECTRONIC DATA PROCESSOR Filed Dec. 9, 1960 :56 Sheets-Share?l 2 118V +121/ 102 6a: JZ 6,62 02 Je 100 g jam` Jaa 10Q 10a (zu 7- 06 105 Z5 105 105 1 Dec. 15, 1964 c. H. PRoPsTER, JR., ETAL 3,161,855

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Dec. l5, 1964 C. H. PRoPsTER, JR., ETAL ELECTRONIC DATA FROCESSGR Filed Dec. 9. 1960 36 Sheets-Sheet 4 Dec. l5, 1964 c. H. PROPSTER, JR., ETAL. 3,161,856

ELECTRONIC DATA PROCESSOR .'56 Sheets-Sheet 5 Filed DeC. 9, 1960 .Il I lll. .l 'IIININHINW Immmx|||| Dec. l5, 1964 c. H. PRoPsTER, JR., ETAL 3,161,856

ELECTRONIC DATA PROCESSOR 36 Sheets-Sheet 6 Filed Dec. 9, 1960 A Z50 KC "6V PA .Z850 av H H T L UM IUUJL' Dec. 15, 1964 c. H. PRoPsTER, JR., ETAL 3,161,856

ELECTRONIC DATA PROCESSOR 36 Sheets-Sheet '7 Filed Dec. 9. 1960 blug@ QQU .NRNUQ Dec. 15, 1964 c. H. PRoPsTER, JR., ETAL 3,161,856

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ELECTRONIC DATA PROCESSOR Filed Dec. 9, 1960 56 Sheets-Sheet 12 Dec. l5, 1964 c. H. PRoPsTER, JR., ETAL 3,161,856

ELECTRONIC DATA PROCESSOR 36 Sheets-Sheet l5 Filed Dec. 9, 1960 Dec. 15, 1964 c. H. PROPSTER, JR., ETAL 3,161,856

ELECTRONIC DATA PROCESSOR "56 Sheets-Sheet l 4 Filed DeC. 9. 1960 Nhww Nimm

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ELECTRONIC DATA PROCESSOR Filed Dec. 9, 1960 56 Sheets-Sheet l5 Dec. l5, 1964 c. H. PRoPsTER, JR., ETAL 3,161,856

ELECTRONIC DATA PROCESSOR 56 Sheets-Sheet 16 Filed Dec. 9. 1960 Gum NNW Dec. 15, 1964 c. H. PRoPsTER, JR.. ETAL 3,161,856

ELECTRONIC DATA PROCESSOR 36 Sheets-Sheet 17 Filed Dec. 9, 1960 NcH..

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Dec. 15, 1964 C. H. PROPSTER, JR.. ETAL ELECTRONIC DATA PROCESSOR 36 Sheets-Sheet 18 Filed Dec. 9, 1960 Dec. l5, 1964 c. H. PRoPsTER, JR., ETAL 3,161,856

ELECTRONIC OATA PROCESSOR Filed Deo. 9, 1960 36 Sheets-Sheet 20 I? T5110 H52 61110 'W04 l(1'1 554 Caza-e 61119 90 11x12 al, 

1. IN A SERIAL, STORED-PROGRAM, DIGITAL COMPUTER HAVING AN INSTRUCTION SEQUENCING SECTION FOR CONTROLLING THE EXECUTION OF SINGLE-ADDRESS AND ONE-PLUS-ONE ADDRESS INSTRUCTIONS, SAID ONE-PLUS-ONE ADDRESS INSTRUCTION CONSISTING OF TWO GROUPS OF DIGITAL SIGNALS, A FIRST GROUP OF A GIVEN ONE-PLUS-ONE ADDRESS INSTRUCTION SPECIFYING AN OPERATION TO COMPARE THE ABSOLUTE VALUE OF A GIVEN NUMBER WITH THE ABSOLUTE VALUE OF A SPECIFIED CONSTANT AND TO BRANCH TO AN ALTERNATIVE SEQUENCE OF INSTRUCTIONS BEGINNING WITH AN INSTRUCTION AT AN ADDRESS SPECIFIED BY A SECOND GROUP OF DIGITAL SIGNALS IF A SPECIFIED RELATION IS PRESENT BETWEEN THE VALUE OF SAID GIVEN NUMBER AND THE VALUE OF SAID SPECIFIED CONSTANT, SAID SPECIFIED CONSTANT BEING REPRESENTED BY A PORTION OF SAAID FIRST GROUP OF DIGITAL SIGNALS WHICH GROUP INCLUDES TWO DISTINCTIVE DIGITAL SIGNALS, THE COMBINATION COMPRISING: A MEMORY SECTION HAVING A PLURALITY OF SEQUENTIALLY ACCESSIBLE MEMORY LOCATIONS; A FIRST AND SECOND REGISTER; A THIRD REGISTER FOR STORING A GROUP OF DIGITAL SIGNALS REPRESENTING SAID GIVEN NUMBER; FIRST MEANS FOR TRANSFERRING SAID FIRST GROUP OF DIGITAL SIGNALS TO SAID FIRST REGISTER INCLUDING A SERIAL BINARY ADDER THROUGH WHICH SAID FIRST GROUP OF DIGITAL SIGNALS IS SERIALLY TRANSFERRED TO SAID FIRST REGISTER; SENSING MEANS FOR DETERMINING THE PRESENCE OF SAID TWO DISTINCTIVE DIGITAL SIGNALS OF SAID FIRST GROUP OF DIGITAL SIGNALS; 